Introduction / Quick RecapPrior reading before our quick recap: [to be updated] by Nebojsa NovakovicThe Xeon E5 (8 core/16 thread) silicon live in living colour - with a 20MB L2, die size of 416mm and a transistor count of ~2.263 billionOverview of the Xeon E5 - basically all the improvements of the Sandy Bridge microarchitecture like AVX and Turbo Boost 2.0 brought to the server/workstation platform
Block Diagram - with 2 QPI links, Quad Channel LRDIMM support and 40 PCIe 3.0 lanes per socket, the Xeon E5 should be a no brainer for high performance workloads
Partitioning of the 32nm planar double-gate transistors Sandy Bridge-EP die
Xeon E5-2600 SKUs ranging from low power quad core variants to the full fledged 8-core 150W monsters
Intel Integrated I/O in a nutshell - integrating traditional north bridge into the CPU and providing DMA access to storage and network controllers for reduced latencies
Unlike earlier Xeons and SNB/SNB-E, we're sad to report that multiplier adjustment is disabled (BIOS values set to read only) and base clock straps are non-existent (frequency only goes up to ~108MHz) across the current stepping. We sure hope Chipzilla changes their mind (since traditionally it has never been obstructed, albeit not officially supported) or maniac SR-X overclockers/high frequency traders are going to be turned away.
Quad channel IMC in the Xeon E5 also supports DDR3 LRDIMM (evolution of FB-DIMM but pin compatible with regular UDIMM) that allows densities up to 768GB (24 x 32GB modules)