About FSB:DRAM Ratio...

[chang87]

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Hello Istoryans,

Question lang about aning FSBRAM Ratio...

Unsa ni xa? Nosebleed lagi ko ani aie... wahahah

Mine is currently running @ 3:8...

Is that good or bad? heheh





Thx daan!

[pauloray]

unsa model sa imong Processor ug Mobo?

[kent213]

Basta interconnection between sa processor ug ram..hahaha

blurred pa pud kaau akong understanding ani.. hehehe

nice TS par ma enlighten pud ang uban..

[EarlZ]

Its the ratio used by the memory controller to determine a speed which it runs, example on my Q6600 im using na 1:1 ratio at 400FSB, this means that the processor FSB and MEM speed runs at 400Mhz ( since it is ddr2 its 400x2) resulting in a DDR2-800.
Say I run at 100FSB, @ 1:2 ratio that means 100FSB processor and 200 for the Mem, other motherboards/bios versions refer to this as the memory divider.

Another example for DDR3, if you use a i7 with 133BLCK and you have a DDR3-2133Mhz then you would need to use a higher memory divider or ratio to actually make the memory run at 2133 instead of the intel defined or mobo official limit of 1600 or 1866.

Im pretty poor with math so I cant tell if 3:8 is bad or just default but I can tell you if you can provide to me your processor used and if its overclocked to a specific FSB.

[chang87]

Im pretty poor with math so I cant tell if 3:8 is bad or just default but I can tell you if you can provide to me your processor used and if its overclocked to a specific FSB.

bai earlz, im using an AMD Athlon II X4 640 OC'ed @ 3.465Ghz w/ 231 FSB...

[poldopunk]

i asked the same question years ago. i'll try to answer it as simple as i can:

sakto ingon ni EarlZ nga ratio to determine the speed at which the memory runs. to put it in another perspective, it is a delay put into place para imong front-side bus ma synchronize sa imong rated memory speed (JEDEC specs) rated memory speed (assuming JEDEC spec) ma synchronize sa front-side bus. i can go into details pero samot kang maglibog. :/

edit:

if anyone wants a detailed explanation, let me know and i'll post everything i know about the FSB-based architecture but don't take my word for it kay dili man tawn ko engineer. i just read a lot (forums, manuals, review sites, datasheets) and compare data kay dili man sad kasaligan kung usa ra ka source imong basahon.

[chang87]

edit:

if anyone wants a detailed explanation, let me know and i'll post everything i know about the FSB-based architecture but don't take my word for it kay dili man tawn ko engineer. i just read a lot (forums, manuals, review sites, datasheets) and compare data kay dili man sad kasaligan kung usa ra ka source imong basahon.

cge boss! go go go!

[poldopunk]

sige-sige, i don't think i can finish it in one post let alone one night so i'll start with the basics (definition of terms).

clock -- if you're not familiar what a clock is, think of a sine wave. a complete rotation is a cycle, and cycles are measured in Hertz so 2.4 GHz, giga meaning billion and hertz meaning cycles. intel doesn't actually use Hertz, they call it mega transfers or giga transfers but let's leave it at that.

double-pumped or DDR/double data rate or quad-pumped/QDR or quad data rate is the transmission of data in a given cycle, usa ka sine wave for example. check out the highlighted red on the illustration here, kanang naka highlight, diha ang transfer ug data within the front-side bus in a given clock. ang DDR kay mao na ang mga duha ka highlighted red sa babaw.

i am telling you this because in my opinion, mao ni ang foundation sa fsb-based computing, halos tanan aspects diri ga depend.

moving forward, sa FSB-based motherboards or sa Intel Nehalem architecture, ang clock generator naa sa motherboard. in fact, early overclockers use to de-solder the low-rated clock generator and replace it with a higher one, thus giving the overclock results since out of spec naman. the clock generator doesn't just generate a clock value nga iyang gusto, the processor determines this. for example, ang E6xxx nga processor have a base clock ID nga 266 MHz so inig insert nimo sa processor into the socket, ang pins niya mo determine unsa ang base clock sa processor which will now be used to determine unsa nga clock ang i-generate sa clockgen.

still with me before i proceed?

[poldopunk]

what the heck, let me just proceed anyway.

ang porma sa motherboard in an FSB-based architecture is like this:



to make things simpler focus on the following: CPU, front-side bus, memory controller hub (MCH), memory bus and memory slots. kani nga mga components in my opinion are divided into 2 with the memory controller at the middle. Ang usa ka division ang CPU, FSB ug MCH while the other is the MCH, memory bus ug memory slots.

so assuming nga imo nang gitaud imong E6xxx based Core 2 Duo which has a 266.66~ MHz base clock. the front-side bus is designed to be quad pumped, meaning upat ka data transfers in a cycle so:

266.66~ x 4 = 1066 rounded off. mao ni imong makit-an nga specs sa motherboard nga "supports 1066 FSB". it is referring to this lane between the processor and the memory controller.

on the other hand, we have the memory which is double data rate. so assuming the memory nga gigamit is DDR2-533, we simply have to divide the 533 by 2 to get the actual memory speed so:

533 / 2 = 266.5 MHz

mao ni silbi ang mura'g base clock sa memory. (DON'T CALL IT BASE CLOCK, EXAMPLE RA NA).

still with me on this?

edit:

this example is a 1:1 ratio. meaning ang 266 MHz nga front-side bus, mao pud ang speed nga ginagamit sa memory which is 266 MHz (DDR2-533).

[poldopunk]

ok, if you've reached this far you're still interested so let me proceed:

WHAT IF ang imong memory nga gipalit kay rated for DDR2-800?

800 divided by 2 = 400 so ang base nga speed sa memory si 400 MHz

using the previous post as a formula would mean nga imong memory will run at 533 MHz or DDR2-533 so nausik ang remaining supported frequency kay underclocked imong memory?

not necessarily. the MCH will read the specs in the memory (assuming JEDEC standards) and make adjustments para imong FSB, maka accomodate sa higher memory frequency. this is called a memory divider. if it turns out that the base memory frequency is lower than the fsb frequency, it will use a memory multiplier.

so, ang 3:8 sa imong FSB : DRAM ratio means that for every 3 parts nga operation sa FSB, the memory will have to do 8 para mag abot ilang speed.

ganahan pa unta ko himoon siyang algebraic equation para mklaro pero giduka na ko, trabaho pa ko ugma. if anyone can translate this to such, i'd greatly appreciate it.

questions? ask away.

edit: with the new architecture, this has slightly changed but still has the same principle so kung makasabot ka ani, dali ra pud nimo masabtan ang current architecture.